1. Field
Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a semiconductor device having buried bit lines and a method for fabricating the same.
2. Description of the Related Art
Most semiconductor devices include transistors. For example, a semiconductor memory device represented by a DRAM includes a memory cell having a MOSFET. In general, in a MOSFET, since source/drain regions are formed in the surface of a substrate, a planar channel is formed between the source region and the drain region. Such a general MOSFET is thus referred to as a planar channel transistor.
As improvements in degree of integration and performance are continuously demanded for a semiconductor memory device, a technology for fabricating a MOSFET faces physical limitations. For example, as the size of a memory cell shrinks, the size of a MOSFET shrinks, which causes the channel length of the MOSFET to be shortened. If the channel length of a MOSFET is shortened, data maintaining properties are likely to deteriorate, whereby the characteristics of the memory device may be degraded.
In consideration of these problems, a vertical channel transistor (VCT) has been suggested in the art. In the vertical channel transistor, junction regions are formed at the respective ends of a pillar, and any one of the junction regions is connected with a bit line. The bit line is buried in a trench defined between pillars, so it is referred to as a buried bit line (BBL).
Two adjacent memory cells each including a vertical channel transistor (VCT) and a buried bit line (BBL) are adjacent to one buried bit line (BBL). Therefore, the buried bit line (BBL) is formed in a space (for example, a trench) between two adjacent memory cells, and an OSC (one-side-contact) process is performed to connect one memory cell with one buried bit line (BBL). The OSC process is a process for allowing each buried bit line (BBL) to be brought into contact with any one of two adjacent memory cells. Thus, the OSC process is also referred to as a single-side-contact (SSC) process. Generally, in a memory device that adopts a planar channel transistor, in order to connect a planar channel transistor with a bit line, a contact plug process with a high aspect ratio is required. In contrast, in the case of adopting a vertical channel transistor and a buried bit line, since the vertical channel transistor and the buried bit line may be brought into direct contact with each other, a contact plug process is not required. Therefore, the parasitic capacitance of the bit line may be reduced.
FIG. 1 is a cross-sectional view illustrating buried bit lines according to the conventional art.
Referring to FIG. 1, a plurality of body lines 14, which are separated by trenches 13, are formed on a substrate 11. The body lines 14 are formed through performing an etching process for the substrate 11, using mask patterns 12. A passivation layer 15 is formed on the sidewalls of the body lines 14 and on the surfaces of the trenches 13. Open parts 17 are defined in the passivation layer 15 through an OSC process. Each open part 17 opens any one sidewall of each body line 14. Buried bit lines 16 are formed in the trenches 13. The buried bit lines 16 are connected with the body lines 14 through the open parts 17. Each buried bit line 16 is connected with any one of two adjacent body lines 14. While not shown in the drawing, the upper portion of each body line 14 includes a pillar in which source/drain regions and a channel for a vertical channel transistor are formed.
Referring to FIG. 1, in order to connect each buried bit line 16 to the sidewall of any one of the adjacent body lines 14, an OSC process is adopted. In order to realize the OSC process, various methods such as a liner layer and a tilt ion implantation process, an OSC mask process and the like have been proposed.
However, these methods fail to form a uniform and reproducible OSC structure due to difficulties in processing. Also, as high integration further proceeds, the distance between adjacent buried bit lines 16 becomes narrow and parasitic capacitance (CB) between adjacent buried bit lines 16 increases. Since the buried bit lines 16 are brought into contact with the body lines 14, the parasitic capacitance (CB) between buried bit lines 16 is substantially the same as the capacitance between the body line 14 and the buried bit line 16. Because the distance between adjacent buried bit lines 16 becomes narrow, the parasitic capacitance (CB) increases markedly. If the parasitic capacitance (CB) between buried bit lines increases in this manner, the operation of a device may become impossible.
Also, in the conventional art, since the body lines 14 are formed in consideration of the height of the pillar that includes a channel region, high aspect ratio etching is required as an etching process for forming the body lines 14. Accordingly, because the trenches 13 are formed with a sufficient height (referred to as the reference symbol H) to include the height of the pillar, a concern is raised in that the body lines 14 are likely to lean.